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Message
From: kuoping<kuoping@m...>
Date: Mon May 14 05:53:13 CEST 2007
Subject: [oc] patch of SoC Debug Interface
Hi,
I found the dead code on the SoC Debug Interface. The attached file is patch. Any suggestion?
dbg_cpu.v: line #966
else if (addr_len_cnt_end && (!addr_len_cnt_end) ...
should be
else if (addr_len_cnt_end && (!addr_len_cnt_end_q) ...
dbg_wb.v: line #1157
else if (addr_len_cnt_end && (!addr_len_cnt_end) ...
should be
else if (addr_len_cnt_end && (!addr_len_cnt_end_q) ...
-------------- next part --------------
diff -rNu dbg_interface/rtl/verilog/dbg_cpu.v dbg_interface/rtl/verilog.new/dbg_cpu.v
--- dbg_interface/rtl/verilog/dbg_cpu.v 2004-04-08 22:15:10.000000000 +0800
+++ dbg_interface/rtl/verilog.new/dbg_cpu.v 2007-05-14 11:01:41.189886800 +0800
@@ -923,7 +923,7 @@
begin
status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
end
- else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
+ else if (addr_len_cnt_end && (!addr_len_cnt_end_q) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
begin
status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
end
diff -rNu dbg_interface/rtl/verilog/dbg_wb.v dbg_interface/rtl/verilog.new/dbg_wb.v
--- dbg_interface/rtl/verilog/dbg_wb.v 2004-04-02 01:21:22.000000000 +0800
+++ dbg_interface/rtl/verilog.new/dbg_wb.v 2007-05-14 11:03:16.391183900 +0800
@@ -1157,7 +1157,7 @@
begin
status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
end
- else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
+ else if (addr_len_cnt_end && (!addr_len_cnt_end_q) && curr_cmd_rd_comm)
begin
status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
end
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