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Message
From: H. Peter Anvin<hpa@z...>
Date: Mon May 7 08:28:40 CEST 2007
Subject: [oc] Ethernet tri-mode
Matt Ettus wrote:
>
> I am trying to work with the ethernet_tri_mode core. I am having some
> trouble with it and can't reach the original author.
>
> The core instantiates a dual ported RAM which is based on the altsyncram
> Altera primitive, which is obviously not portable. I am trying to
> replace it with one in plain verilog. However, I am not familiar with
> the altsyncram primitive, so I don't know if the author intended
> synchronous or asynchronous read ports. If synchronous, it is also not
> clear if it should be read-through or not. If anyone can help me figure
> out what the attached altsyncram instantiation does, it would be most
> appreciated.
>
altsyncram always have registered inputs (address and data.) The
instantiation you showed has unregistered outputs.
-hpa
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