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Message
From: Richard Herveille<richard@h...>
Date: Wed Apr 25 11:23:41 CEST 2007
Subject: [oc] RMW and Wishbone
Bus arbiter MAY assign the bus to another requesting master while CYC is
asserted.
There are more (smaller) issues in the RevB.3 Wishbone spec.
Are you willing to work on updating it?
Richard
-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Matt Ettus
Sent: Wednesday, April 25, 2007 9:39 AM
To: Discussion list about free open source IP cores
Subject: Re: [oc] RMW and Wishbone
Richard Herveille wrote:
> Hi Matt,
>
> This depends on the implementation of the bus switch/arbitration
controller.
> The Wishbone SOC Bus spec does not describe how to write the interconnect,
> it just provides the means to do so.
>
I don't think this has anything to do with a particular implementation
of the interconnect. The question is, if a master holds cyc_o high, is
the interconnect ALLOWED to take access away in the middle of the bus
cycle.
If yes, then the lock signal is necessary to perform an RMW cycle, and
the appendix section about RMW cycles is incorrect.
If no, then the lock signal is not necessary.
The whole point of a standard bus is that it works the same no matter
what is connected to it. The way a master initiates an RMW cycle should
not depend on how the interconnect was designed. Otherwise you need to
redesign your master for every different kind of interconnect.
Matt
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