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Message
From: ken.cambpell at edgewater.ca<ken.cambpell@e...>
Date: Thu Apr 19 20:05:04 CEST 2007
Subject: [oc] VHDL Test Bench package release
A couple of weeks ago the initial release of the VHDL Test Bench
package was submitted to CVS. It is released under the "Other" Catagory.
http://www.opencores.org/projects.cgi/web/vhld_tb/overview
This package has been used by me for 10+ years for my verification
efforts. The designes verified by the system provided by this package
range from VHDL models of various complexity to full blown ASIC's.
Applications ranging from simple generators to DSP blocks.
It is hoped that others can find the package as useful as I have over
the years. Also, this is proven to work and has been made to be
portable. Though the portablity has yet to be proven behond Modelsim
and Leapfrog tools.
If there are any questions or comments, please feel free to post up or
mail me.
Sckoarn ;(
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