OPENCORES.ORG

hi mostafa,

Iam trying to do a similar project using i2c protocol...where i hav to
implement the master core using vhdl...
did u get successful results so that u can help me because i got struck
somewhere.....

Mostafa-3 wrote:
> 
> Hello,
> 
> I am trying to get a VHDL testbench running with the VHDL I2C core and
> and Verilog I2C slave model. I've implemented the WISHBONE master as a
> simple state machine. I tried to follow the same steps in the Verilog
> testbench in CVS but somehow that is insufficient. The I2C master
> drives the SCL and SDA lines from 'H' to '0' and '0' to 'H' as
> expected but the slave does not appear to respond to the commands. The
> slave SDA line is perpetually at 'Z'.
> 
> At this point I am really not sure what might be wrong and am in
> desperate need of some help. The source files are available here:
> 
> http://m.afgani.googlepages.com/WB_I2C.zip
> 
> Thanks in advance,
> Mostafa
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
> 
> 

-- 
View this message in context: http://www.nabble.com/I2C-core-VHDL-testbench-tf3502675.html#a10002852
Sent from the OpenCores - IP Cores mailing list archive at Nabble.com.