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Message
From: H. Peter Anvin<hpa@z...>
Date: Thu Apr 12 02:52:18 CEST 2007
Subject: [oc] recent i2c questions
Matt Ettus wrote:
> After further perusing the code it appears that this is done by the core
> itself. It wasn't clear from the docs.
Well, the HDL for an open drain and for a tristate which is never "1" is
identical in both Verilog and VHDL. In Verilog, you would write either as:
assign output = output_active ? 1'b0 : 1'bz;
Even if you explicitly instantiate an open drain buffer, any FPGA
synthesizer will simply instantiate it as a tristate buffer with its
input tied to zero.
So, there is nothing the core has to do.
-hpa
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