|
Message
From: Wesley J. Landaker<wjl@i...>
Date: Thu Apr 12 01:36:15 CEST 2007
Subject: [oc] recent i2c questions
On Wednesday 11 April 2007 17:07, Matt Ettus wrote:
> I just joined the list, but looked over the recent i2c discussion. I
> have a related question which I don't believe was answered.
>
> The directions in the I2C documentation say to use a tri-state pin for
> SCL and SDA, but I thought that an open-drain was necessary. My
> thinking is this:
[...]
> Am I missing something here? The only other option I can see is to
> de-assert the OE signal when you want to send a 1, thus turning off the
> drive and simulating an open drain, but I don't know if that works in
> practice. Most FPGAs don't have real open-drain outputs, do they?
Yes, this the way to do it, it's not that hard. You drive low for a low, and
don't drive at all for a high.
Obviously the entire bus needs to be pulled up. And if you want to actually
be compliant, as opposed to just doing some ad-hoc messing around, make
sure you actually meet the I²C electrical as well as timing specifications
for the bus speed you are targeting.
--
Wesley J. Landaker <attachment.pgp
|
 |
Browse
