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I'm getting the same problem that DR is getting. SDA and SCL are not

1.	The documentation is better than other documentation for IP's I have paid for.  In fact, it's clear, concise and very useful.
2.	The code works as advertised.  It compiles perfectly, and runs out of the box.
3.	I personally have used the code in 3 different tool sets with no issues.

Tool issues?

With all this apparent issues with the core, I think we should be thanking Richard for the code.  Thanks Richard for a great core.

Stan Hodge
Honeywell Electronics and Lighting

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On Behalf Of richard@h...
Sent: Tuesday, April 03, 2007 9:14 PM
To: Discussion list about free open source IP cores
Subject: Re: [oc] I2C Issue

Hi guys,

The provided testbench works; it has been tested on synopsys vcs, cadence
ncsim, and modelsim. These are the 3 leading simulators.
The core works; I have confirmed reports of over 50 companies using the
core in their designs; a few more if you add those companies using the
commercially available versions. And it works out of the box!!!
I added a makefile (for ncsim only) that runs the testbench.
Combining the core (in rtl), the testbench (in bench), the makefile (in
sim/bin), and the documentation (in doc) you should be able to get this
running. Ok admitted you need to understand the wishbone bus interface; so
download that spec too.

I heard complaints about the doc, people not being able to find the
testbench, people not being able to hook everything together.
To be honest, this indicates either a lack of knowledge of using IP cores
(which is fine, but then don't blame the core), or just a general lazyness
in searching opencores.

The testbench is self checking; this means it is not waveform oriented.
Forget about checking waveforms with your eyes. This might work for the
i2c interface but not for bigger IP cores. Instead the testbench initiates
transfers and automatically checks the core (i.e. the status of the i2c
bus and registers). Obviously the testbench does wiggle the sda and scl
lines ;)

Down to the stupid questions;
1) Did you run the provided testbench or are your running your own?
2) Did you create the open-drain outputs using the tri-state buffers as
described in the doc. Please don't tell me you don't understand the doc as
it provides a graphical representation and the actual code to implement
the buffers (both in vhdl and verilog).
3) Did you pull-up SDA and SCL in the testbench?

Some notes:
1) There is a typo in the VHDL code; scl_pad_i <= sda should of course be
sda_pad_i <= sda. But you should have figured that out.
2) No idea why there's still a documentation folder. It should be removed.

Richard

> I'm getting the same problem that DR is getting.  SDA and SCL are not
> toggling.  Has anyone been able to get it to work or is this how the test
> bench works?  Richard has done a great job putting this together, I just
> wish he would've included an explicit readme file and a simulation result
> for reference.
> Steve
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>

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