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From: Mostafa<m.afgani@g...>
Date: Mon Apr 2 12:35:59 CEST 2007
Subject: [oc] I2C core VHDL testbench
The Verilog testbench is the one from CVS:

( i2c_slave_model.v, tst_bench_top.v, wb_master_model.v)
http://www.opencores.org/cvsweb.shtml/i2c/bench/verilog/

(i2c_master_bit_ctrl.v, i2c_master_byte_ctrl.v, i2c_master_defines.v, i2c_master_top.v,
timescale.v)
http://www.opencores.org/cvsweb.shtml/i2c/rtl/verilog/

I simply created a new project and added all of those files. Then I ran a behavioral
simulation of tst_bench_top.v using ISE simulator.

-Mostafa

----- Original Message -----
From: D R<heedaf@e...>
To:
Date: Mon Apr 2 09:04:51 CEST 2007
Subject: [oc] I2C core VHDL testbench

> I've been working on this thing for weeks and I can't figure it
> out. Since you have some success, could I ask for your help with
> the verilog side? I'm using ISE 9.1 also, is there anyway that you
> would send me the verilog project and then maybe I can figure out
> what the heck I'm doing wrong. I'd sure appreciate it. If you
> can't, how did you add the test bench in the project? I put the
> "test_bench_top" on top of the
> "wb_master_model" all in one .v test benc file. I put the
> slave in its own .v file. Everything compiles correctly but the
> start command (8'h90) doesn't seem to be written. If I can get this
> running - then I'll try and give you a hand.Thanks,Dewayne--- On
> Mon 04/02, &lt; attachment.html
>
>