Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: m.afgani at gmail.com<m.afgani@g...>
Date: Mon Apr 2 02:18:49 CEST 2007
Subject: [oc] I2C core VHDL testbench
Hello,

I am trying to get a VHDL testbench running with the VHDL I2C core and
and Verilog I2C slave model. I've implemented the WISHBONE master as a
simple state machine. I tried to follow the same steps in the Verilog
testbench in CVS but somehow that is insufficient. The I2C master
drives the SCL and SDA lines from 'H' to '0' and '0' to 'H' as
expected but the slave does not appear to respond to the commands. The
slave SDA line is perpetually at 'Z'.

At this point I am really not sure what might be wrong and am in
desperate need of some help. The source files are available here:

http://m.afgani.googlepages.com/WB_I2C.zip

Thanks in advance,
Mostafa

Follow up	Author
[oc] I2C core VHDL testbench	Srikanth24