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Message
From: larytet.46060479 at bloglines.com<larytet.46060479@b...>
Date: Tue Feb 20 18:22:23 CET 2007
Subject: [oc] data base for ASIC/FPGA develpers
I did not think that the tool will generate (or even parse) Verilog files.
I though mainly about synchronization between designers, verification team
and software team. The central point of the tool is generating of datasheet(s)
I do not throw away the idea of actually parsing Verilog files and looking
for some tags, but i think that DocBook already does this. I guess it is possible
in the future to integrate the engines. Meanwhile I want to limit the scope
of the problem and focus the efforts in solving the main problem - replacing
of the Access data base.
>All:
>
>I've used a tool like this based on
exceed....
>with a bunch of perl scripts to generate RTL. I
>hated it.
There is no question that design
>effort was INCREASED rather than lessened
by the
>"tool". There is some real value in forcing
>standards - register
designs - register
>documentation standards... but that can be done
>with good design practices.. It does not need to
>be enforced by tools.
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