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Message
From: Richard Herveille<richard@h...>
Date: Tue Nov 21 18:14:19 CET 2006
Subject: [oc] Suggested extension to wishbone bus
Hi Miha,
| You can implement one wishbone classic interface for reading
| and one for
| writing in device
| B. DAT_I and DAT_O signals are optional, so it should be
| allowed. Than it is
| up to interconnect
| to allow simultaneous access to both ports.
That's my point. I don't see a need to define an extension considering what
you can already do with the current spec. Unless it addresses some
fundamental functionality.
[rih] Fully agreed, you can achieve the same with 2 wishbone interfaces.
The extension is merely meant to directly support an architecture with split
read/write buses.
How are dat_i and dat_o optional? Without them, there's not much bandwidth?
;)
[rih] dat_i and dat_o are optional. Some cores need only read or write
access to the wishbone bus. I can even imagine cores that don't need any
data at all. For example a watch-dog that monitors bus activity would only
check CYC (and STB) and assert ERR_O if there isn't any activity for a long
time.
Richard
./ks
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