Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: tera.bits at gmail.com<tera.bits@g...>
Date: Thu Nov 16 21:53:58 CET 2006
Subject: [oc] Verilog AHB Master Slave ???????

Hi

Anyone has ahb master/slave models in verilog /
in this site i found some ahb generator in vhdl but no proper
vhdl2verilog tools.
please let me know if you have any of the above

regards