OPENCORES.ORG

'H' is generated by the pullup in the top level (verilog) module of the

All true.
Keep in mind this is an IP and as thus does not include any IO buffers.
I need to check for '1' in the core.
However the i2c bus requires external pull-ups.
It's the tesbench that should take care of the conversion from 'H' to '1'.
Using the many techniques discussed here.

Richard

> 'H' is generated by the pullup in the top level (verilog) module of the
> testbench, and propogated down to the I2C core via inout ports in the
> hierarchy of the (VHDL) design.

Normal practice (as I expect you already know or have just worked out!) 
is never to let anything except 0, 1, or X into the chip. This 
complicates the code and may cause simulation mismatches between the RTL 
and the netlist. You need to do this at the input buffer. If you look at 
the Xilinx models for their input buffer (in unisim_VITAL.vhd), for 
example, you'll find that it's basically:

  O <= TO_X01(I) after 0 ps;

This problem doesn't normally come up in the ASIC world, because you 
instantiate all I/O buffers. However, if you're just writing behavioural 
code and relying on the tool to infer I/O buffers, then it's a good idea 
to put this code on your inputs or IOs at the top level.

[isn't it a bit late in your part of the world?!]

RT
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores