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Message
From: Richard Tierney<rt-opencores@c...>
Date: Thu Oct 26 11:02:21 CEST 2006
Subject: [oc] which the RTL code of I2C core is corrected
Mark McDougall wrote:> 'H' is generated by the pullup in the top level (verilog) module of the
> testbench, and propogated down to the I2C core via inout ports in the
> hierarchy of the (VHDL) design.
Normal practice (as I expect you already know or have just worked out!)
is never to let anything except 0, 1, or X into the chip. This
complicates the code and may cause simulation mismatches between the RTL
and the netlist. You need to do this at the input buffer. If you look at
the Xilinx models for their input buffer (in unisim_VITAL.vhd), for
example, you'll find that it's basically:
O <= TO_X01(I) after 0 ps;
This problem doesn't normally come up in the ASIC world, because you
instantiate all I/O buffers. However, if you're just writing behavioural
code and relying on the tool to infer I/O buffers, then it's a good idea
to put this code on your inputs or IOs at the top level.
[isn't it a bit late in your part of the world?!]
RT
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