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From: Mark McDougall<markm@v...>
Date: Thu Oct 26 10:36:30 CEST 2006
Subject: [oc] which the RTL code of I2C core is corrected
Richard Tierney wrote:

> A more compact/standard solution is to use a strength stripper from
> std_logic_1164:
>
> sSCL <= to_X01(scl_i);
> sSDA <= to_X01(sda_i);
>
> This converts a std_(u)logic value to 'X', '0', or '1', forcing L/H to
> 0/1, and preserving X's.

Ah yes, thank you!!!

> It's interesting that you have an 'H', though - presumably this is an
> external signal in the testbench? If not, how does an 'H' get into the
> device?

'H' is generated by the pullup in the top level (verilog) module of the
testbench, and propogated down to the I2C core via inout ports in the
hierarchy of the (VHDL) design.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266