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Message
From: Richard Herveille<richard@h...>
Date: Wed Oct 25 08:18:23 CEST 2006
Subject: [oc] which the RTL code of I2C core is corrected
The i2c VHDL port is a translation of the verilog core, provided for the
benefit of the VHDL community.
The verilog core is fully tested. Any changes to the verilog port are
backported to the VHDL version.
The core is tested numerous times, though not as thorough as the verilog
port. As the verilog port is the developer port, whereas the vhdl port is
merely a translation. However the last changes were very trivial so I didn't
check, which I obviously should have :p. It's fixed now.
The code you download should be clean.
Anyways it's always a good idea to thoroughly check whatever IP you receive.
Richard
-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Mark McDougall
Sent: Wednesday, October 25, 2006 4:44 AM
To: Discussion list about free open source IP cores
Subject: Re: [oc] which the RTL code of I2C core is corrected
Mark Murray wrote:
> There are syntax errors in the latest VHDL code; two lines with "End
> If" are missing the terminating semicolons.
Richard, given the nature of the above error, can I assume that the
latest VHDL version (rev 1.14) hasn't been tested at all? Not even in
the testbench?
I'm not complaining in any way, I'd just like to know the state of what
I'm downloading. It's less work for me if I know that it has already
been verified, otherwise I need to increase the coverage of my testbench.
Thanks for all your work on this and numerous other cores!
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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