OPENCORES.ORG

Hello,
    Here is a synthesizable 32 bit divider written in Verilog. You can 
modify it easily for 16 or 8 bits easily if you want.

thanks
Adil

=================================================
// Unsigned/Signed division based on Patterson and Hennessy'salgorithm.
// Description: Calculates quotient.  The "sign" input determines whether
// signs (two's complement) should be taken into consideration.

module divide(
       ready,
       quotient,
       remainder,
       dividend,
       divider,
       sign,
       clk
  );

   input         clk;
   input         sign;
   input [31:0]  dividend, divider;
   output [31:0] quotient, remainder;
   output        ready;

   reg [31:0]    quotient, quotient_temp;
   reg [63:0]    dividend_copy, divider_copy, diff;
   reg           negative_output;

   wire [31:0]   remainder = (!negative_output) ?
                             dividend_copy[31:0] :
                             ~dividend_copy[31:0] + 1'b1;

   reg [5:0]     bit;
   wire          ready = !bit;

   initial bit = 0;
   initial negative_output = 0;

   always @( posedge clk )

     if( ready ) begin

        bit = 6'd32;
        quotient = 0;
        quotient_temp = 0;
        dividend_copy = (!sign || !dividend[31]) ?
                        {32'd0,dividend} :
                        {32'd0,~dividend + 1'b1};
        divider_copy = (!sign || !divider[31]) ?
                       {1'b0,divider,31'd0} :
                       {1'b0,~divider + 1'b1,31'd0};

        negative_output = sign &&
                          ((divider[31] && !dividend[31])
                        ||(!divider[31] && dividend[31]));

     end
     else if ( bit > 0 ) begin

        diff = dividend_copy - divider_copy;

        quotient_temp = quotient_temp << 1;

        if( !diff[63] ) begin

           dividend_copy = diff;
           quotient_temp[0] = 1'd1;

        end

        quotient = (!negative_output) ?
                   quotient_temp :
                   ~quotient_temp + 1'b1;

        divider_copy = divider_copy >> 1;
        bit = bit - 1'b1;

     end
endmodule

============================================

----Original Message Follows----
From: "Richard Herveille" <richard@h...>
Reply-To: Discussion list about free open source IP cores 
<cores@o...>
To: "'Discussion list about free open source IP cores'" 
<cores@o...>
Subject: RE: [oc] synthesizable divider
Date: Fri, 20 Oct 2006 19:08:01 +0200

Check the dividers project on opencores.

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of xiaodongjin@h...
Sent: Friday, October 20, 2006 6:36 PM
To: milacn@s...; cores@o...
Subject: Re: [oc] synthesizable divider

hello, Currently I am working on a project that needs division
algorithm, but i have no idea about it, how can i implement a
synthesizable divider using vhdl or verilog? Would you like to give me
some kinds of example?

thanks a lot!
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