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Message
From: Richard Herveille<richard@h...>
Date: Fri Oct 20 19:08:01 CEST 2006
Subject: [oc] synthesizable divider
Check the dividers project on opencores.-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of xiaodongjin@h...
Sent: Friday, October 20, 2006 6:36 PM
To: milacn@s...; cores@o...
Subject: Re: [oc] synthesizable divider
hello, Currently I am working on a project that needs division
algorithm, but i have no idea about it, how can i implement a
synthesizable divider using vhdl or verilog? Would you like to give me
some kinds of example?
thanks a lot!
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