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Message
From: FatalLicorne at yahoo.com<FatalLicorne@y...>
Date: Thu Sep 28 13:55:58 CEST 2006
Subject: [oc] Searching I2S core
Hello Macro,
Here is my work:
I receive SPDIF and convert to I2s , then i convert serial data of I2s
to parallel. Do you have any idea ?
----- Original Message -----
From: piotrek_trela@y...<piotrek_trela@y...>
To:
Date: Sat Jan 22 13:30:07 CET 2005
Subject: [oc] Searching I2S core
> Hello Marco
>
> It seems that I've sent this message to the wrong person at first.
> Sorry
> about that. I would like to ask you if you managed to obtain some
> more
> detailed information about TLV320AIC23B Codec. I need to know what
> is
> the BCLK frequency in Master Mode. Data sheet is rather poor and it
> doesn't explain clearly how to use this device. Data sheet suggest
> that
> the maximum frequency is 50Mhz but it has nothing to do with 12MHz
> crystal.
> Thank you in advance for help
> Peter
> ----- Original Message -----
> From: castell@e...<castell@e...>
> To:
> Date: Sat Dec 6 23:27:18 CET 2003
> Subject: [oc] Searching I2S core
> > Hello Hansi.
> >
> > I was in your shoes a few months ago when I needed exactly the
> same
> > to interface to the TLV320AIC23B audio CODEC from Texas
> > instruments.
> > I have completed my project and have successfully used the I2S
> > interfaces that I designed.
> > However, I have implemented the I2S receiver and transmitter
> as
> > separate entities, because in my design they needed to be so.
> Since
> > I
> > just finished the project a couple of days ago, there isn't a
> whole
> > lot of
> > documentation others that all my comments in the code.
> > I will be more than happy to provide the VHDL code to you.
> > I designed them with FIFO interfaces, so they don't really
> need to
> > be
> > memory mapped, you only read from or write to the FIFOs
> > Let me know if you are interested.
> > Regards,
> > Marco
> > Marco Castellon <castell@e...>
> > University of Alberta, Edmonton CANADA
>
>
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