LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Mark McDougall<markm@v...>
    Date: Thu Sep 28 08:15:03 CEST 2006
    Subject: [oc] IrDA SIR - not working???
    Top
    Mark McDougall wrote:

    > Has anyone else come across this???
    > Can the author comment?

    I've rewritten the decoder module and have gotten my simulation working.
    There's also potential problems introduced when dynamically switching
    the negation for TX/RX (at least after setting the baud rate), since
    clearing the FIFOs won't reset the receiver shift register. This could
    potentially be a problem on a real system when you need to negate RX in
    the core at startup - though thinking about it it should be safe if you
    set negation before setting the baud rate in the UART itself.

    Also, the documentation states that the MCR is R/W, when it is in fact
    write-only.

    Would still like to hear of others' experiences.

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266

    ReferenceAuthor
    [oc] IrDA SIR - not working???Mark McDougall

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.