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Message
From: Mike Delaney<mmdst23@g...>
Date: Sat Jul 1 20:15:20 CEST 2006
Subject: [oc] Any one have ddr controller for MT46V32M16 -6
The differential clocks should be generated in the FPGA logic using DCMs to
get the phase differences, and I think either the DCMs will also give an
inverted output, or you can use an inverter for it. That said, I had the
same issue of the chip/package I was using was not supported by it, but it
that was 2 years ago. Check the Xilinx docs and support website. You
should be able to get it working.
Mike
On 1 Jul 2006 11:24:36 -0000, subin <attachment.htm
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