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Message
From: joseph_gassman at agilent.com<joseph_gassman@a...>
Date: Fri Jun 30 23:33:37 CEST 2006
Subject: [oc] I2C test bench timing violations?
I'm getting a timing violation when I run as close to 100 kHz SCL rate as
possible (33.33MHz system clock, prescale=0x42). I have translated
your testbench into VHDL. The only violation that I get is at the
repeated start when reading from the I2C slave model (tSU;STA), but
my application would be capable of violating the tL_SCL as well.
>From what I can see, an easy fix would be to insert 'f' and 'g' states
for "start", and insert an 'e' state for the other conditions, and adjust
the outputs in these states accordingly, and adjust the prescale value
to be 6x SCL. This should provide a little extra margin, especially for
tH_SCL and tSU;STO, which currently have zero slack at exactly 100kHz
SCL rate. However, I have not tried this yet, and there may be details
that I don't see yet.
What resolution do you run your simulation at?
Thanks,
Joe
----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Wed Feb 2 17:09:50 CET 2005
Subject: [oc] I2C test bench timing violations?
> You're the first user to report these violations.
> I can imagine that you get these when your resolution is too small.
> The prescalers are simple counters that scale the system clock down
> to 5x
> the scl clock.
>
> It would be best if you send me information about the system clock,
> and your
> prescale register settings.
>
> Cheers,
> Richard
>
> _____
> From: cores-bounces@o...
> [mailto:cores-bounces@o...] On
> Behalf Of Jeff Hanoch
> Sent: Wednesday, February 02, 2005 4:05 AM
> To: cores@o...
> Subject: [oc] I2C test bench timing violations?
> I'm trying to simulate the I2C controller using the code I just
> downloaded from CVS.
> I'm getting many timing violations specifically setup on the start
> condition (SDA falling to SCL falling is 4.2us instead of 4.7us).
> Also
> getting SCL width errors (3.6us instead of 4.0us). The expected
> numbers
> in the timing checks agree with the published I2C spec.
> Has anyone else had problems with the timing of this core? It's
> going
> into an ASIC very quickly and I'm a little concerned.
> I've changed the prescaler to run at 85KHz instead of 100KHz and
> this
> seems to fix most of the violations (I'm still getting 1 setup
> violation).
> Are these "real" issues I need to fix, or are they not an
> issue with the
> I2C parts on the market today?
> Any input would be appreciated.
> Thanks,
> Jeff
> P.S. Here's the violation I see at 85KHz...
> # status: 187062600 generate 'start', write cmd 20 (slave
> address+write). Check invalid address
> # ** Error: i2c_slave_model.v(342): $setup( negedge sda
> &&& scl:1881 us,
> negedge scl:1885200 ns, 4700 ns );
> # Time: 1885200 ns Iteration: 1 Instance: /tst_bench_top/i2c_slave
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