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Message
From: Fabrizio Fazzino<fabrizio@f...>
Date: Wed Jun 28 21:17:03 CEST 2006
Subject: [oc] Re: Wishbone Memory Harness
Hello!
I've modified Rudi's model by myself, I come from VHDL but I have
to admit that there's no competition with Verilog... $readmemh()
system task is GREAT if compared with VHDL I/O that is a
nightmare!
Here you can get the modified file:
http://www.fazzino.it/pub/mem_harness.v
As you can see the main changes are:
- 64-bit wide address and data buses;
- memory content initialization from hex file;
Cheers,
Fabrizio
Fabrizio Fazzino wrote:
> Hello,
> I was looking for a Memory Harness with Wishbone Slave interface
> written in Verilog. I've found the one written by Rudi time ago
> but it can only be initialized with random data.
>
> As far as you know, is there any Wishbone slave model that can
> be initialized with the content of an ASCII file? I've been
> looking a lot inside several OC projects but I could not find
> one suitable.
>
> Thanks in advance,
>
> Fabrizio
>
--
============================================
Fabrizio Fazzino - fabrizio@f...
Fazzino.IT - http://www.fazzino.it
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