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Message
From: Fabrizio Fazzino<fabrizio@f...>
Date: Mon Jun 26 11:54:50 CEST 2006
Subject: [oc] Wishbone Memory Harness
Hello,
I was looking for a Memory Harness with Wishbone Slave interface
written in Verilog. I've found the one written by Rudi time ago
but it can only be initialized with random data.
As far as you know, is there any Wishbone slave model that can
be initialized with the content of an ASCII file? I've been
looking a lot inside several OC projects but I could not find
one suitable.
Thanks in advance,
Fabrizio
--
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Fabrizio Fazzino - fabrizio@f...
Fazzino.IT - http://www.fazzino.it
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