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Message
From: Avi Blanka<avi_blanka@y...>
Date: Wed Jun 21 18:02:34 CEST 2006
Subject: [oc] operating the UART in Oopen core Or1200
Dear All,
I have a problem with OR1200 cores, I operated it in the board and
trying to operate the UART , I hope you can help me to figure it out:
1. I connected ram size 4kx32 to WB0 slave and connected the
uart to wb5 (slave and working with uart 32bit data size),
When I operated the Uart, I saw that I have trampling over
the command area, Is it a SW problem or is the problem in the
ram.ld file? and how to solve this problem?
2. How can I know when it is a data cycle or when its fetch cycle?
Is there some signal which indicate which kind of cycle it is?
Best Regards,
Avi.B
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