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Message
From: wxs<wanxuesong_china@y...>
Date: Wed Apr 12 11:09:16 CEST 2006
Subject: [oc] how to use wb_builder
hi,all
i am a newbie to use opencores.
now i want to build a wishbone bus.my tools is wb_builder.i can build a VHDL
file,but i wish a verilog file.i change the file type to verilog,but make
erroe.
and all of entity in one file.so i cant compile the file.how can i do it.
please help me!
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