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I have a few questions about the core simple_spi_top.v

tullio.grassi@r... wrote:
> I have a few questions about the core simple_spi_top.v
>>From line 267 there is:
> 
>               begin
>                   bcnt  <= #1 3'h7;   // set transfer counter
>                   treg  <= #1 wfdout; // load transfer register
>                   sck_o <= #1 cpol;   // set sck
> 
>                   if (~wfempty) begin
>                     wfre  <= #1 1'b1;
>                     state <= #1 2'b01;
>                     if (cpha) sck_o <= #1 ~sck_o;
>                   end
>               end
> 
> This is inside an always.
> Here sck_o is assigned twice with two concurrent statements. 
> Is this correct and unambiguous ?

Short version:
It might be OK, depending on which tools you use, but I would certainly
not recommend it.

Longer version:
According to the 'original' Verilog LRM, the order of multiple
non-blocking assignments, a) with intra-assignment delay, and b) ending
up in the same time slot, cannot be guaranteed. Ie the outcome of the
code above would be 'random' (see page 8-8 of "OVI Verilog hardware LRM
1.0" (my file is called ovi.verilog.lrm.1.0.pdf)).

But, in the newer Verilog 2001 standard, it seems that this has been
resolved in cases where there are a clear order of execution (as in the
example). I.e. the code above will work as intended in a Verilog
2001-compatible simulator (see section 9.2.2, p. 123, of IEEE
P1364-2005/D3 (a draft revision of IEEE std 1364-2001) (my document is
called 1364-2005_D3.pdf)).

Note however that repeated nonblocking assignments to the same variable
_without_ intra-assignment delay are OK with all tools that I know of.

> In Verilog all statements in a begin/end block are executed in parallel.
> So I guess that when the "if" conditions are true, it is undetermined
> which statement will be implemented by the synthsizer.

Since delay controls are discarded by normal synthesis tools, I would
guess that most synthesis tools would produce the expected results.

Best regards
Gunnar Dahlgren
ASIC designer, Axis Communications AB, Sweden

> There is a similar problem in the same module:
> the signals wfre and rfwe are assigned twice with two concurrent
> statements.
> 
> Comments ?
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