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From: rgnanadavid at gmail.com<rgnanadavid@g...>
Date: Fri Mar 31 21:02:09 CEST 2006
Subject: [oc] Memory Controller COre
Hi all,

I'm a graduate student. I have chosen the Advanced MEmory
Controller Core for Verfication using CTL. I've chosen to use the Memory
TIMING Controller block in it. I'm not able to follow certain signal
definitions and functions from the verilog file. CAn u help me with some
detailed documentation for that part..

regards
Rakesh