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From: Mike Delaney<mmdst23@g...>
Date: Fri Mar 31 22:36:56 CEST 2006
Subject: [oc] DDR SDRAM controller core
I think that that core will only work in Xilinx Virtex-2 and Virtex-4
FPGAs, and possibly Spartan3/3Es. It uses a lot of Xilinx specific
primatives from what I rembember.
Mike

On 3/30/06, Stefan Zorn <s_zorn@h...> wrote:
> Hallo everybody!
>
> I just started with VHDL programming.
> I try to set up the DDR SDRAM core on a Altera StratixII FPGA by using
> QuartusII Software.
>
> Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to
> compile the projekt, i'd ned them. unisim is used in reset and for the bufg.
> Has someone an idea how i can solve this
> Problem?
>
> best regards
>
> Stefan
>
>
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