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Message
From: Mikhail Matusov<misoma@r...>
Date: Fri Mar 31 16:56:28 CEST 2006
Subject: [oc] DDR SDRAM controller core
On Fri, 31 Mar 2006 07:56:42 +0000
"Stefan Zorn" <s_zorn@h...> wrote:
SZ> Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to
SZ> compile the projekt, i'd ned them. unisim is used in reset and for the bufg.
SZ> Has someone an idea how i can solve this
SZ> Problem?
You need to replace them with the similar Altera modules or modify the
code to get rid of them altogether. Depending on which signal requires
bufg it is possible that the synthesizer will assign it automatically
for you. Alternatively it can usually be done with attributes.
/Mikhail
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