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Message
From: Stefan Zorn<s_zorn@h...>
Date: Fri Mar 31 09:56:42 CEST 2006
Subject: [oc] DDR SDRAM controller core
Hallo everybody!I just started with VHDL programming.
I try to set up the DDR SDRAM core on a Altera StratixII FPGA by using
QuartusII Software.
Quartus has no UNISIM librarys and can't use the libs from Xilinx. But to
compile the projekt, i'd ned them. unisim is used in reset and for the bufg.
Has someone an idea how i can solve this
Problem?
best regards
Stefan
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