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Message
From: Arnim Laeuger<arnim.laeuger@g...>
Date: Sat Mar 18 15:36:47 CET 2006
Subject: [oc] AC97 system integration
Hi!> Any idea why "The Wishbone clock must be at least 2x bit_clk_pad_i"?
This is my interpretation of the circuit built around bit_clk_r in
ac97_soc.v. bit_clk_r samples the AC97 clock on bit_clk_pad_i with the
Wishbone clock. This can only work reliably when wclk has at least
twice the frequency of the sampled signal.
Initially, I did not recognize this and got GO/NOGO designs depending on
the frequency of wclk. For a design where wclk was close below 2x
bit_clk_pad_i, there was much noise on the speaker output. Sometimes no
signal at all which turned into noisy audio when I touched some of the
analog components connected to the V_REF pin on LM4550. Another design
with wclk around 20 MHz worked perfectly fine. Nearly drove me mad...
> I had noise problem with my own AC97 controller on LM4550: when I had
> speaker and headphone both plugged, the speaker output is ok. But
> when I unplugged the headphone, the speaker output because noisy
> instantly; The heaphone output was always noisy regardless whether
> the speaker is connected or not.
*Might* be similar to my observation. I mean, messing with the analog
domain often reveals effects that are hard to diagnose at first sight.
What frequency is your wclk?
Cheers
Arnim
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