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Message
From: Guy Hutchison<ghutchis@g...>
Date: Fri Mar 3 18:50:46 CET 2006
Subject: [oc] a chinese engineer's question on PLL
In general, if you don't understand how a PLL works, you're probably
dealing with it from a digital designer's perspective. For that, it is
simplest to view a PLL as a black box that outputs a clock with a frequency
that is a multiple of its input clock frequency.
PLLs use an error-feedback circuit to figure out when their output clock is
at the correct frequency, and this circuit takes some time to converge.
After convergence, the PLL said to be "locked" to its input frequency.
Most PLLs will have a "lock" or "ready" signal coming out of them, and are
also spec'ed to have a maximum unstable time before they achieve lock.
Because some PLL designs can drift in and out of lock, the safest technique
is to use a two-phase reset, where the first phase releases the PLL from
reset, and starts an internal timer. When the timer expires, the second
reset signal is released, which releases core logic from reset.
Wikipedia has an extensive article on the subject:
attachment.htm
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