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Message
From: Mike Delaney<mmdst23@g...>
Date: Mon Feb 27 19:16:31 CET 2006
Subject: [oc] DDR SDRAM Question
Actaully, that interface is only for Xilinx Virtex-2/V2 Pro FPGAs (it
may work for Spartan3/3Es and Virtex-4s). It should have a tri-state
layer, but I think that has to go in your highest design layer.
I never got it to work (but that was over a year ago), so unfortunatly
that's about the extent of what I know about it.
Mike
On 2/27/06, Guy Hutchison <ghutchis@g...> wrote:
>
>
> On 2/26/06, Shehryar Shaheen <shehryar.shaheen@u...> wrote:
> > The DQS port should be 'inout' ( 'in' for reads and 'out' for writes ) or
> maybe I'm missing something.
> > If any user or the Author himself can answer , I'll appriciate.
>
> Just a guess, but cores developed for ASIC use typically have a port triplet
> (in/out/enable) for bidirectional ports, since tristate functionality is
> implemented in the pad ring.
>
> - Guy
>
>
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
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