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Message
From: Arnim Laeuger<arnim.laeuger@g...>
Date: Sun Feb 19 12:59:41 CET 2006
Subject: [oc] AC97 system integration
Hi all,I've been using Rudi's AC97 controller for a couple of projects and
found it's working very well. In the first place, I was in doubt about
compatability issues as there are many codec chips around and not all of
them might have been used with this core up to now.
Surprisingly, I've had only very few issues when integrating the whole
AC97 stuff using a very simple configuration. There's just an FSM
stimulating the Wishbone interface doing the basic initialization of the
core and the codec. After initialization, the FSM performs regular
writes to the FIFO to send 8-bit audio samples to the codec.
Well, in the future I might step to more complex applications and would
like to share experience with other users of the AC97 controller core.
I've identified three things that are worth mentioning concerning system
integration.
Xilinx' Project Navigator seems to have problems determining the
resulting hierarchy from all the conditional instantiations. For the
time being, I fixed the verilog RTL to my specific implementation but
that's not very nice. Is there a way that PN can handle the definitions
in ac97_defines.v properly?
The National Semi LM4550 requires a SYNC high time of 1.3 us for warm
reset instead of 1.0 us. Just had to adjust AC97_RES_SIG in
ac97_defines.c accordingly.
The Wishbone clock must be at least 2x bit_clk_pad_i. Sometimes, I got
excessive noise on the speaker lines when this rule was violated.
Tweaked the circuit in ac97_soc.v to account for lower WB clocks.
Do you have further input/comments? Is the whole AC97 story really
plug'n play; What should one be aware of?
Cheers
Arnim
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