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Message
From: Rudolf Usselmann<rudi@a...>
Date: Thu Oct 20 14:26:41 CEST 2005
Subject: [oc] Small CPU architectures
On Mon, 2005-10-17 at 18:37 +0200, maliredyrvr@r... wrote:
> I want to do my research on mixed s/n design bcoz i am the person
> related to (VLSI)Masters degree holder . I have sufficient knoweledge
> to do research or project on mixed s/n design(which includes both
> analog and digital).If u r having any offer for that particulars pls
> reply sooon
> ur's
> Msreddy
Hmm, you are a "Masters degree holder" ? And you do not know
how to spell "because" and "you" and "are" and "please" ?
And that should be "knowledge" I guess ... Sad, sad sad ...
So I guess your Verilog would look something like:
alws (for always)
asgn (for assign)
cs (for case)
etc, etc, etc
--
rudi
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