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Message
From: Michael Geng<vhdl@M...>
Date: Tue Oct 4 17:27:24 CEST 2005
Subject: [oc] Extensions to single_port asynchronous memory model
Hi Robert, hi all,I would like to add the following 2 extensions to the single_port memory model for simulating
asynchronous memories:
1. Make the address and data buses unconstrained instead of defining their widths in a package.
After that it will be possible to use multiple instances of this model with different address or
data port widths within the same design.
2. Trigger it with any change on the data or address buses or on the rnw signal. This is the
behaviour real asynchronous memories have. The present model is only triggered on rnw. Reading
multiple addresses without a transaction on rnw presently doesn't work.
The single_port project is found under Memory core / Single Port ASRAM. Speciality of this model
is an efficient use of simulator memory. 1.9GB of memory of my PC are used while I'm simulating my
design which contains a model for 512kB of memory. With the LinkedList architecture of the
single_port model less than 500MB are used.
You can already view the updated documentation at
http://www.michaelgeng.de/single_port.html
and download the tared and ziped sources with all changes from
http://www.michaelgeng.de/vhdl.tar.gz
if you want to see them in advance.
I would prefer to become maintainer for this project because then I can check in the changes
myself.
Michael
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