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Message
From: InvalidError at gmail.com<InvalidError@g...>
Date: Tue Sep 27 19:56:45 CEST 2005
Subject: [oc] Bus delay - FPGA
There is a simple fix for that: you need to pack registers in your
IOBs and this may require adding an extra register level.
I am guessing you are doing something like:
counter_o <= counter_s; -- route the counter register to outputs
process (clk)
begin
if (rising_edge(clk)) then
counter_s <= counter_s + 1; -- increment the counter register
end if;
end process;
The proper way of doing it for most situations is:
process (clk)
begin
if (rising_edge(clk)) then
counter_s <= counter_s + 1; -- increment the counter register
counter_o <= counter_s; -- if this signal drives IOBs, the synthesis
tool should treat it as a register and pack it in IOBs if the target
device has IOB registers... and all current FPGAs I know of do.
end if;
end process;
The proper way implies that the observable value is always one behind
the register's current value and you have to build the rest of your
design to account for that. Routing inside FPGAs is somewhat slow,
complex and unpredictable. FPGAs are designed for synchronous designs,
they have plenty of D-latches and I recommend that you use them -
particularly the IOB ones since they do not cost you any core logic
and help weed out lots of nonsense in the static timing analysis.
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