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Message
From: Guy Hutchison<ghutchis@g...>
Date: Sat Sep 24 01:43:14 CEST 2005
Subject: [oc] Bus delay - FPGA
That's a natural property of buses; the signals will never transition
simultaneously. Whatever is reading those signals should be registered (I
assume you mean "registered" when you say "latched") with sufficient time
for the signals to settle.
In short, you're clearly trying to do something strange here, and you
haven't described what it is, and that's most likely the real problem, not
that the signals are transitioning perfectly. Perhaps if you describe what
you're trying to do with these signals we can help you.
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