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Dear Cargnini,

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1. yes it make difference i founded this two simple explanations in
2cpu.com, to say in simple form:
"first unregistered unbuffered will have better performance
There really isn't a lot to say from a technical perspective about
unbuffered memory. It's what the vast majority of PCs on the planet use.
Essentially, with unbuffered memory the chipset deals directly with the
memory itself. There is nothing in between the two parties as they
communicate."

"Registered modules have additional components (registers) placed
between the incoming address and control information and the SDRAM
components. These modules are typically used in Servers due to their
added reliability (they place much less of an electrical load on the
memory controller and therefore make it possible to have as many as 16
or 32 modules in a large system).
~From what I've read, a stick of memory that contains registers will
actually hold data for one full clock cycle before it's passed on. A
small performance hit is generally incurred as a result. Registered
memory is all about scalability and stability."
so it make difference in final delay of your application, but you need
reliability or performance this is the question

2. oops i don't understood how it happens too, but ..... configuration
mig ?, you can't configure the data path width ?? number of banks ?
something like this ? (i know that you can), so maybe modifying some
parameters could help the generation, other way i don't know what it
could be

3. forget the mig pin editor make your own ucf file
xjf77@y... wrote:
| Dear Cargnini,
|       I would like to discuss some problems with regards to MIG007. I
| would like to generate the ddr sdram controller for for ML310 circuit
| onboard 256MB DIMMs. I have the following problems.
| 1. MIG007 currently support only unbuffered DDR SDRAM. While my
| onboard DIMMs is registered, dose this affects the operation?
| 2. In my case, I am wondering which memory type I can select
| (component or dimms?). If select DIMMs, then SDRAM part data width is
| restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310
| use only 32 bits of DDR SDRAM data pins. How dose it come? Feel
| puzzled on it.
| 3. MIG007, as Anna said, seems to be not compatible with the real
| circuit board pin out constraints, i.e., some real DQS pins are not
| allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to
| neglect the Pin Editor using my own ucf file, I think. Otherwise we have
| to manually modify the generated ucf file to adapt to the board pin
| connection.
|     That's it!
| Thanks a lot in advace.
| regards,
| Jeff
|
| ----- Original Message -----
| From: Luís Vitório Cargnini<cargnini@m...>
| To:
| Date: Thu Aug 11 06:15:45 CEST 2005
| Subject: [oc] DDR SDRAM controller
|
|

| _______________________________________________
| http://www.opencores.org/mailman/listinfo/cores

- --
Thanks && Regards
Luís Vitório Cargnini
IEEE Member
Mastering @ PUCRS - Electrical Engineer - Microelectronics
Sponsored by CNPQ
Computer Science Bachelor
OpenCores Member <www.opencores.org>
EuropeSwPatentFree <http://EuropeSwPatentFree.hispalinux.es>
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