OPENCORES.ORG

Dear Cargnini,

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

wow excuse i saw only now this mail i'll read it and answer back in some
minutes

xjf77@y... wrote:
| Dear Cargnini,
|       I would like to discuss some problems with regards to MIG007. I
| would like to generate the ddr sdram controller for for ML310 circuit
| onboard 256MB DIMMs. I have the following problems.
| 1. MIG007 currently support only unbuffered DDR SDRAM. While my
| onboard DIMMs is registered, dose this affects the operation?
| 2. In my case, I am wondering which memory type I can select
| (component or dimms?). If select DIMMs, then SDRAM part data width is
| restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310
| use only 32 bits of DDR SDRAM data pins. How dose it come? Feel
| puzzled on it.
| 3. MIG007, as Anna said, seems to be not compatible with the real
| circuit board pin out constraints, i.e., some real DQS pins are not
| allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to
| neglect the Pin Editor using my own ucf file, I think. Otherwise we have
| to manually modify the generated ucf file to adapt to the board pin
| connection.
|     That's it!
| Thanks a lot in advace.
| regards,
| Jeff
|
| ----- Original Message -----
| From: Luís Vitório Cargnini<cargnini@m...>
| To:
| Date: Thu Aug 11 06:15:45 CEST 2005
| Subject: [oc] DDR SDRAM controller
|
|

| _______________________________________________
| http://www.opencores.org/mailman/listinfo/cores

- --
Thanks && Regards
Luís Vitório Cargnini
IEEE Member
Mastering @ PUCRS - Electrical Engineer - Microelectronics
Sponsored by CNPQ
Computer Science Bachelor
OpenCores Member <www.opencores.org>
EuropeSwPatentFree <http://EuropeSwPatentFree.hispalinux.es>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.1 (FreeBSD)

iD8DBQFDE87mII4c9KZOcnoRAs27AJwI8JZIJ1Z4XkxSLd6+DcgtgdrloQCfXxw6
rLdM8XJWvQzeE38ENW+VzXc=
=5APc
-----END PGP SIGNATURE-----