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Message
From: shreshthakumar at gmail.com<shreshthakumar@g...>
Date: Sun Aug 7 23:25:42 CEST 2005
Subject: [oc] FIR
Sir/Madam
I am new in FPGA . I took to implement FIR in FPGA . I decided Direct
form fir so blocks are symmetric and easy to add taps, Konstant
Coefficient Multiplier , decimators and Delays. I 've written code in VHDL
and simulated in modelsim and synthesised in Xilinx ISE5.1 . I chose
spartan 2 144pin FPGA. As i havent downloaded it yet to any FPGA so
my question is that whether I need more blocks to be made (e.g.
memory interfacing, as any data voice or image will be firstly stored in
some ram , so is RAM present in FPGA board?. what should i look
forward to , so that I can test my FIR filter with reeal set of datas.
shresthakumar@g...
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