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Message
From: prabu at rri.res.in<prabu@r...>
Date: Fri Aug 26 07:39:43 CEST 2005
Subject: [oc] DDR SDRAM controller
Hi,
Can you give more details on the kind of problems that you are
facing. Can you cut and past the error messages. We will see
and let you know if we could interpret and give some suggestions.
- tp
----- Original Message -----
From: ada at cwazy.co.uk<ada@c...>
To:
Date: Wed Aug 10 12:06:43 CEST 2005
Subject: [oc] DDR SDRAM controller
> Hi all!
> Curently I am a Master student and I am working on my master
> thesis.
> And for some purposes I have to write or adapt a DDR SDRAM memory
> controller (for Xilinx Virtex II board with xc2v4000 FPGA). First I
> wanted to adapt DDR SDRAM memory controller from opencores
projects
> but there is no support and noone ansers questions:( Then I found
> the
> Memory Interface Generator (mig007) tool from Xilinx and generated
> a
> memory interfece. Unfortunatelly I have lots of errors during
> translation (in ucf file after I defined all pins acording to my
> board
> ucf file). I asked Xilinx but there is no answer. I do not know
> what
> to do. Could someone help me? I would be glad to have any help.
> Best,
> Anna
>
>
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