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Message
From: Luís Vitório Cargnini<cargnini@m...>
Date: Thu Aug 11 06:15:45 CEST 2005
Subject: [oc] DDR SDRAM controller
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first upgrade your ise to 7.1.03i latest version, second yes i tested on
board of memec with Spartan3-1500, i tested on board, and simulated too
using a new tb made by me, instantiate generate a clock an put addr,
data, we and see what you get.
Well to do your interface and test if it working put the DDR controller
write some addr on memory than read this address, or put a second
hardware module that could read the memory outside fpga like a
microcontroller and see what you get, a design kit will really help in
this time, develop hw without a dev kit is a little .....too risk, is
the better words. PLEASE verify your ucf, and verify the source code
generated as i said i remember, mig generated defectuous code, check it
signal by signal instantiation and interconnection by one, don't forget
to check all of them first and depurate it.
Anna D. Ashley wrote:
| Good evening,
|
| thank you very much indeed for an answer.
|
| I think I should say some more words about my problem. I have an ucf
| file which was provided with my board and in order to map all pins
| correctly I used "Pin editor" of the mig007 tool. According to "How to
ring
| use" all red coloured pins are allowed to select for DQS from
|
|
- --
Thanks && Regards
Luís Vitório Cargnini
IEEE Member
Mastering @ PUCRS - Electrical Engineer - Microelectronics
Sponsored by CNPQ
Computer Science Bachelor
OpenCores Member <www.opencores.org>
EuropeSwPatentFree <http://EuropeSwPatentFree.hispalinux.es>
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iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCgr84m
j89WR136v8IxvknnUPKBXtM=
=XFbt
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