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Message
From: mwiesbock at gmail.com<mwiesbock@g...>
Date: Thu Jul 28 20:30:17 CEST 2005
Subject: [oc] New to Wishbone,
any very simple verilog examples of data exchange?
Hi,
Im relativly new to FPGAs in general, and have started a project
trying to get the ethernet core with wisbone to work on my Virtex-4
board. I have the wishbone specs PDF file, and the cores, pretty much
everyhting I need that I know of.. tho im a little lost at putting it
all together. Is there any examples that anyone knows of that just has
a really basic syscon, with a slave and master hooked up so I could
really see how how it all fits together. The documentation is pretty
good, tho.. for me specificy, seeing code works better then just
reading about it. Or perhaps even better, is there even a ethernet
core written in verilog that does not come with wishbone (just for the
time being so I can get the ethernet part of the board working better).
Sorry if this isnt the right place to post this, but ive been trying
to get this thing up and running, and for whatever reason i just cant
get it all worked out in my head, almost seems to be just too much
information at once since this is all new to me, and not really sure
on what to pay attention to, and what not to, etc.
Thanks again for your time,
Mark
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