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Message
From: foryst at uiuc.edu<foryst@u...>
Date: Fri Jun 10 19:15:34 CEST 2005
Subject: [oc] hdl designer xilinx flow with verilog
Whenever I use hdldesigner and a core that uses a defines file, When I
go to compile it says "cannot open 'include blah.v" or something like
that. I've had this happen to me before, and my workaround was to
just copy contents of blah.v and replace the include file. But thats
really ugly for this paticular core so I'm trying to find out the proper way
to do this. Thanks in advance.
** Error: C:\hds_projects\ION2/Wishbone_RS232/hdl/uart_rfifo.v(151):
Cannot open `include file "uart_defines.v".
Jamey
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