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From: Nicolas Boulay <nico@s...>
Date: Mon, 24 Nov 2003 19:27:50 +0000
Subject: Re: [oc] verilog or vhdl

Le Lundi 24 Novembre 2003 13:51, Tom Hawkins a écrit :
> On Monday 24 November 2003 03:33 am, Richard Herveille wrote:
<...>
> project.  I was surprised to learn that Verilog was originally
> created as a simulation language -- the name Verilog is short for
> "Verifying Logic".   At that time synthesis was an afterthought and
> didn't come along until years later.  I wonder what Verilog would
> look like today if it was originally designed for synthesis.
>

That was the same primary goal of VHDL.

> -Tom
>
> > Oh and btw. There is an extension to VHDL that allows you to do
> > true analog simulations. It's just that we (as DIGITAL) engineers
> > never use it.
> >

VHDL-AMS ? but there is a verilog counter part.

nicO
> >
> > Richard

Reference	Author
RE: [oc] verilog or vhdl	Richard Herveille
Re: [oc] verilog or vhdl	Tom Hawkins

Follow up	Author
RE: [oc] verilog or vhdl	Richard Herveille