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From: Joachim Strömbergson<Joachim.Strombergson@I...>
Date: Mon, 20 Oct 2003 09:44:04 +0200
Subject: Re: [oc] "makedep" for verilog

Aloha!

Rudolf Usselmann wrote:
> Is there the equivalent of "makedep" for verilog ?
> 
> "makedep" or sometimes "mkdep" creates a dependency
> resolution list for makefiles. Would be useful to
> have something similar for Verilog ...

Vera has a makedep-lookalike that generates Makefiles for it's verification 
runs. This might not help you though.

Google help me find a small Perl script that does basically what makedepend 
does. You should be able to adapt that script to Verilog or at least use it as 
a starting poing for a Verilog aware makedepend:

http://freshmeat.net/search/?q=makedepend&section=projects&x=0&y=0

Good thinking btw.

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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Reference	Author
[oc] "makedep" for verilog	Rudolf Usselmann

Follow up	Author
Re: [oc] "makedep" for verilog	Rudolf Usselmann