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Message
From: Joachim Strömbergson<Joachim.Strombergson@I...>
Date: Fri, 26 Sep 2003 08:41:39 +0200
Subject: Re: [oc] Small CPU architectures
Aloha!
H. Peter Anvin wrote:
> I think RISC is the way to go for small size.
Define what size you are talking about: CPU size, SW code (program) size, data
size or all of the above?
A well structured RISC can be implemented in very few number of gates. On the
other hand, old CISCs like z80, 6502, 8051 etc are by todays standards measly,
normally just a few kGates, which is an acceptable cost for programmable
control with good SW tool support.
A simplified RISC with fixed sized instruction words generally means that the
program code will be bigger than a CISC counterpart. A little bit dependant on
the efficiency of the instruction set and slightly alleviated by the greater
numer of registers in the RISC which in some applications makes the RISC code
much better. But there is a good reason why ARM have Thumb instructions, IBM
have toyed with hardwired code compression and ARC, Tensilica etc all support
some sort of instruction subsets, reduction.
If you are really interested in small size - both CPU size and SW code size
then you should instead look into stack processors. Check out Phil Koopmans
old but still excellent book:
http://www.ece.cmu.edu/~koopman/stack_computers/index.shtml
And, if you *really* want small size, and still want the benefit of
programmable control, I recommend reading Ken Chapmans nice set of articles
about KCPCM - basically what Xilinx calls PicoBlaze:
http://www.xilinx.com/support/techxclusives/techX-home.htm
(I just realised that I have posted about KCPCM before, but it's still good.)
Designing CPUs are fun and a good excercise. But I usually want to use a
standard CPU, even though it eats up a few kGates more is the access to lots
of SW tools. There are several good assemblers, compilers, debuggers, editors
for 8051, HC011, 65xx, z80.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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